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Name: Kunal Shah CWID: 893253773

Analysis and Design of a High Speed Continuous-time Modulator Using ?? the Assisted Op-amp Technique

Abstract: –

In this paper we investigate the use of single bit quantizer in modulator with aim to obtain 11-bit performance in 15MHZ B.W. Here a single bit Continuous time delta sigma modulator (CTDSM) has several advantages over other ADC. Due to single bit quantizer only sign of loop filter o/p is relevant which enables to use high-speed however efficient & feed forward 2-stage op-amp with limited output swing. However here “assisted op-amp” technique is used i.e. to obtain required linearity with low power consumption. At high-speed timing mismatch effects in assisted integrator, which can be potential problem.

Keywords: – Analog-to-digital converter (ADC), continuous-time circuit, continuous-time integrator, delta-sigma, and continuous time delta sigma modulator

Introduction: –

A CTDSM has three main important component – A loop filter H(z), A clocked quantizer, A feedback digital-to-analog converter (DAC). The quantizer is strongly non-linear circuit in a linear system, which makes the behavior of ?? modulator very complicated to investigate analytically. However the basic idea of ?? modulator is that the analog input signal is modulated into a digital whose spectrum approximates that of the analog input well in a narrow frequency range but which is other wise noisy. The noise arises from quantization of an analog signal and the loop filter shapes the quantization noise away from desired frequency range.

CTDSM were the burden of achieving high open loop gain is distributed among several op-amps. As stated earlier the modulator here depends upon o/p of open loop filter op-amp speed requirement are greatly relaxed.

1. Continuous time delta sigma modulator: –

Fig 1(a) Basic CTDSM

The basic principle of this ?? modulator is to enclose a simple quantizer in feedback loop to shape quantization noise such that most noise is shifted out of band, which can be later suppressed by filtering. Here in this figure 1(a) the quantizer has been modeled by additive white noise source Ej(k)

Fig 1(b) Basic CTDSM graph

This graph indicates the T.F knows as Noise TF (NTF) from quantization noise Ej to modulator o/p. From this graph it is apparent that the modulator emphasizes the quantization noise at higher frequency. Then this noise is filtered out reducing total in band quantization noise power in modulator o/p. Input impedance of CTDSM is resistive greatly simplifying the design of device. Further with proper design choice of feedback DAC this modulator have implicit anti-aliasing multibit quantizers in the ?? loop are used for high performance conversion. It has several benefits such as more aggressive NTF can be chosen higher in band SQNR for given oversampling ratio (OSR). If NRZ DAC is used, sensitivity of converter to clock jitter is reduced. But it has few drawbacks as well specially at high speed. 4-bit flash ADC designs are straightforward but quantizer needs to provide an o/p within one clock cycle. This makes it in power dissipation of open loop filter.

Modulator architecture: –

Fig 2 Modulator architecture

This figure is of ?? modulator. A single ended diagram is for simplicity and negative value of resistor (-Rx1,-Rx2,-Ra,-Rc) indicate sign inversion of the signals. According to Lee’s rule max flat behavior of out of band gain 4th order NTF should be max of 1.5 sampling rate is 32 implying an average of 32. For enhanced noise shaping complex zeroes are placed in signal band. This results in peak in band SQNR of 77dB, which is 10dB above the desired SNR. However even if 4 bit quantizer is same, SQNR can be achieved but with sampling rate of only 400MHZ. The loop filter is implemented by cascade of integrators with feed forward. It is direct path added from modulator i/p to loop filter o/p due to which it only process quantization noise and results in small value of integrating capacitor. For low noise and results in small value of integrator use active RC design. In 1st integrator the resistor is implemented using assisted op-amp technique. Weighted addition of integrator o/p is performed using various summing amplifier (A5). Capacitive feeds ins to the last integrator which could have accomplish summation but instead of it a dedicated summing amplifier is used to add integrated o/p. In capacitive summation approach, 4th integrator would be in high-speed path of modulator loop and the feed in capacitor needed to implement summation will result in increased delay. Thus this is more power efficient solution. Due to single bit quantizer o/p of summing amplifier can be scaled without efficient NTF. This implies to the design, as o/p of summing op-amp does not depend to accommodate full-scale swing. Feedback resistor and i/p capacitance of A5 occurs at high frequency, which reduces the delay.

There are other ways to implement DAC such as: –

Switched capacitor DAC: – It makes modulator performance robust to clock jitter. It also results in increased in band thermal noise due to aliasing effect. The linearity needed for 1st op-amp is also increased due to spikes of current resulting from discharge of f/b DAC capacitor. Here NRZ DAC (DAC1) was chosen as f/b DAC. A RZ DAC is sensitive to clock jitter. Therefore NRZ can be implemented with switched cap, which reduces open loop gain around 1st op-amp, which increases excess delay. DAC2 compensates for excess loop delay, which is about 55% of clock period. The peak-to-peak voltage of modulator is 2.4V. All the op-amp here is 2-stage NMOS i/p which results in high speed and also feed forward compensation. Due to assisted op-amp the 1st integrator is almost ideal. Finite B.W and excess delay degrade the stability of modulator. To counter RC time constant, resistor and capacitor are digitally tuned.

Assisted Op-amp integrator and timing skew: –

Fig 3 (a) Effect of non-linearity in CTDSM

Here in fig 3.(a) (a) shows the first order of CTDSM with non linear integrator p(t) denotes the pulse shape of feedback DAC. The operational transconductance amplifier (OTA) in integrator is assumed to be weakly non linear with an o/p current given as I = GmVi – G3Vi3. Effects of OTA are as follows: –

– o/p sequence v1k of modulator with open loop filter excited by input u(t) from fig B

– OTA i/p voltage is denoted by x11t

In fig (c) to determine the effect the non linearity on modulator, the non linear current caused by OTA G3 x11(t)3 is injected into linear modulator with i/p nulled and quantizer by passed. The true in band power spectral (PSD) due to non-linearity can be approximated as V1 k + V3k.

2 keys are taken into consideration: –

Nonlinearity can be thought of manifesting from nonlinear current injected into linear (as from figc). Therefore in band distortion can be reduced by reducing internal swing X1(1)(t) or g3 or both.

The PSD of in band noise due to OTA non linearity is related to PSD G3x1(1) (t)3.

FIG 3 (b) Assisted Op-ampThis figure shows the idea behind assisted op-amp applied to active RC integrator. This op-amp is feed forward with phase margin Gmf . Current flowing integrating capacitor is Vin/R ± Iref. Swings at the internal nodes can be avoided by using assisted currents. This way the current through integrating capacitor is absorbed by the assistant and Vx1(t) and Vx2(t) are zero results in improved linearity. If Vx1(t) = 0 i.e the integrator will remain ideal with very less delay.

Fig 3 (c) NTF ModulatorFig 3 (d) SDSR vs. Skew

Fig 3 (e) Timing Skew

Fig 3 (c) shows NTF modulator with both using op-amp assistance and even without it for 1st integrator. Due to op-amp assistance integrator excess delay is reduced. One issue with assisted op-amp integrator is timing skew between feedback ; assistant DAC current causing Vx1(t) and Vx2(t) to be non zero. This current are proportional to V3x1(t) and V3x2(t). Due to non-linearity the components have very little power at low frequency.

From the figure 3 (d) we can say that the curve is asymmetric about ? = 0 and becomes more so with increased non linearity this is due to overlap capacitance in 2nd stage of feed forward amplifier.

Fig 3 (e) shows the positive timing skew is defined as feedback DAC pulse leading to assistant DAC pulse. The figure shows when skew is -0.15Ts for T ; T1 , IDAC is negative which causes Vx1 = -Vmax. At T=T1, Iasst changes its state early which causes current of 2 IDAC to be drawn from o/p node and for T;T2 by virtual ground concept will attempt to settle at +Vmax . For +ve timing skew the operation is different. For T ; T2 Vx1 = -Vmax and for T3 ; T ; T2 net current of 2IDAC is injected into o/p node since DAC is not changed it’s state which causes Vx1 to increase causing +ve. However for T > T3 it will settle at Vmax.

Circuit Design – Operational Amplifier (Op-amp): –

Fig 4 (a) Op-amp

This circuit is a two-stage design that uses feed forward compensation. This architecture is more efficient when compared to miller compensated design, as power is not wasted during charging and discharging of the capacitor. First stage consists of M1, M2, M3 and M4 as long channel device to lower the 1/f component of input referred noise. The output mode of 1st stage is M5 and M6 they are minimum length devices. M9, M10, M5 and M6 have same VDS . As there is a common mode voltage at output stage the DC gain is not degraded by feedback mechanism. Here M5, M6, M8 and M9 are optimized for speed.

Latch, DAC & Assistant Transconductor: –

Fig 4 (b) Latch Fig 4 (c) DAC

Fig 4 (d) Assistant transconductor

Fig (b) consists of CMOS latch, which has a reset phase. Here the latch output is coupled with C2MOS buffer by delayed version of clock. During the reset phase (?3) the output of latches are shorted which causes differential input of latch to become zero and beginning of Q1 which addresses latch hysteresis. C2MOS reduces the data dependent Q1 jitters and assistant path.

Fig (c) consists of schematic diagram of feedback and assistant DAC. Noise from DAC bias circuitry RC filtered so that it does not contribute significant noise. It is implemented with cascade NMOS & PMOS as current source using differential pair. This helps in compensating current flowing through parasitic capacitor at output of 1st integrator.

Fig 4 (d) shows the schematic of assistant transconductor used to inject Vin/R into op-amp output. This circuit is biased so as to have sufficiently large bandwidth. It is class AB design comprising of complementary common gate M2 & M7. M4 & M9 are same size as M3 & M8 respectively.

5. Future work of CTDSM: –

There are of course number of area in which the CTDSM could be well advanced thus improving their usefulness in a wider range of application.

1. Multibit DAC: – A working high speed multibit design could be significant break through not only they have high resolution and more stable but they improve on clock jitter, sensitivity too.

2. Power consumption: – Power can be reduced through non-bipolar circuit or lower supply voltage while maintaining speed.

6. Conclusion: –

The assisted op-amp technology is originally proposed to improve the linearity of low speed high resolution CTDSM was successfully applied to the design of high speed single bit modulator but at high clock rates timing mismatch between the feedback and assistant DAC can be a potential problem.